ATELIER : Programmation temps réel avec FreeRTOS pour Coeur ARM Cortex-M

Objectifs de cet atelier :
• Acquérir une compréhension globale de l’architecture Cortex-M
• Comprendre la mise en œuvre logicielle du Cortex- M et déboguer
• Gérer les interruptions
• Comprendre l’architecture STM32F2
• Découvrir les notions de temps réel multitâches
• Comprendre les vraies contraintes de temps sur les ressources mutuelles
• Comprendre l’architecture de l’OS FreeRTOS
• Découvrir les différents services et API de FreeRTOS
• Apprendre à développer et déboguer les applications FreeRTOS

PROGRAMME

• First day

Cortex-M Architecture Overview

 V7-M Architecture Overview
 Core Architecture
o Harvard Architecture, I-Code, D-Code and System Bus
o Bit-Banding
o Registers (Two stack pointers)
o States and Privilege Levels
o System Control Block
o Systick Timer
o MPU Overview
 Programming
o Alignment and Endianness
o CMSIS Library
 Exception / Interrupt Mechanism Overview
o Vector Table
o Interrut entry and return Overview
- Tail-Chaining
- Pre-emption (Nesting)
 NVIC Integrated Interrupt Controller
o Exception Priority Management
o Fault escalation
Lab : Becoming familiar with the IDE and clarifying the boot sequence
Lab : Interrupt Management on Cortex-M3 (put in evidence tail-chaining/nesting)

STM32F2 MCUs Architecture Overview

 ARM core based architecture
 Description of STM32F20X SoC architecture
 Clarifying the internal data and instruction paths : Bus Matrix, AHB-lite interconnect, peripheral buses, AHB-to-APB bridges, DMAs
 Memory Organization
o Flash memory read interface
o Adaptive Real-Time memory accelerator, instruction prefetch queue and branch cache
o Sector and mass erase
o Internal SRAMs
 Concurrent access to 112 KB and 16 KB blocks
 SoC mapping
 Flash Programming methods
 Boot Configuration
Lab : Get Metrics for a data copy using the DMA or not

Introduction to Real Time

 Base real time concepts
o The Real Time constraints
o Multi-task and real time
 Introduction to FreeRTOS
 The FreeRTOS source code
o The FreeRTOS architecture and features
o Getting FreeRTOS source code
o Files and directories structure
o Data types and coding style
 Naming conventions
 FreeRTOS on the Cortex/M processors
Lab : Simple FreeRTOS Hello World program

• Second day

Thread safe data structures
 Need for specific data structures
 Thread safe data structures
o Linked lists
o Circular lists
o FIFOs
o Stacks
 Data structures integrity proofs
o Assertions
o Pre and post-conditions
Lab : Build a general purpose thread safe linked list

Element of a real time system
 Tasks and Task Descriptors
o Content of the task descriptor
o List of task descriptors
 Context Switch
Demo : Analyse a Context Switch
 Task Scheduling and Preemption
o Tick based or tickless scheduling
 Scheduling systems and schedulability proof
o Fixed priorities scheduling
o RMA and EDF scheduling
 FreeRTOS Scheduling
o Deterministic preemptive scheduling
 Scheduling strategies
 Cyclic scheduling (RMA)
 Deadline scheduling
o Cooperative scheduling
 Hybrid scheduling

Task Management
 The Task life-cycle
o Creating tasks
o Deleting tasks
o The Endless-loop pattern
 Task Priorities
o Assigning task priorities
o Changing task priorities
 The idle task
o Idle task hooks
 Timing
 FreeRTOS Debug Capabilities (Hook, Trace)
Lab : Managing tasks, get trace information

Memory Management
 Memory management algorithms
o Buddy System
o Best fit / First Fit
o Pools Management
Demo : Write a simple, thread safe, buddy system memory manager
 FreeRTOS-provided memory allocation schemes
o Allocate-only scheme
o Best-fit without coalescing
o Thread-safe default malloc
o Best-fit alloc and free
 Checking remaining free memory
 Adding an application-specific memory allocator
 Memory management errors
o Stack monitoring
o Dimensioning Stack and Heap
Lab : Detect stack overflow

• Third day

Synchronization Primitives
 Introduction
o Waiting and waking up tasks
o Semaphores
o Events
o Mailboxes
 FreeRTOS Binary Semaphores
o Take a Binary Semaphore
o Give a Binary Semaphore
Lab : Synchronizing a task with another one through binary semaphores
 FreeRTOS Queues
o Basic use
 Creation
 Sending on a queue
 Receiving from a queue
o Data management
 Sending compound types
 Transfering large data
Lab : Synchronizing a task with another one through queues

Resource Management
 Mutual Exclusion
o Spinlocks and interrupt masking
o Mutex or Semaphore
o Recursive or not recursive mutexes
o Priority inversion problem
 Priority inheritance
 Priority ceiling emulation
 FreeRTOS Mutexes
o Mutexes and binary semaphores
o Deadlocks
o Priority inversion
o Priority inheritance
Lab : Protect a shared resource using mutexes
 Critical sections
o Critical sections
o Suspending (locking) the scheduler
 Gatekeeper tasks
Lab : Implement mutual exclusion between two tasks with critical sections

Parallelism Problems and Solutions
 Parallel programming problems
 Uncontrolled parallel access
Lab : The producer-consumer problem, illustrating (and avoiding) concurrent access problems
 Deadlocks
 Livelocks
 Starvation
Demo : The dining philosophers problem, illustrating (and avoiding) deadlock, livelock and starvation

Interrupt Management
 Deferred interrupt processing with FreeRTOS
o Tasks with interrupt synchronization
o Using semaphores within an ISR
o Counting semaphores
o Using queues within an ISR
 FreeRTOS interrupt processing
o Writing ISRs in C
o Interrupt safe functions
o Interrupt nesting
Lab : Synchronize Interrupts with tasks

Software Timers
 The Timer Daemon Task
 Timer Configuration
 One-shot / Auto-reload Timer
 Software Timer API
Lab : Implement Soft Timers

Un support de cours (en anglais) est remis à chaque stagiaire.
Assistance technique : une assistance par mail et téléphone est aussi assurée pendant les 3 mois qui suivent la session

INFORMATIONS PRATIQUES

Public visé et prérequis :
• Connaissance des concepts C et de la programmation
• Connaissance de base des processeurs embarqués

Lieu :
CCI Nord Isère Parc Technologique
5 rue Condorcet
38 VILLEFONTAINE

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